As the trend of scaling down integrated circuits continues, the semiconductor industry is forced to consider new techniques for fabricating precise components at submicron levels. This is of particular relevance to the manufacture of memory devices. The expansion of the memory capacity is dependent on the ability to fabricate smaller cells having increased capacitances. Dielectric layers are the foundation to the creation of cell capacitors. As such, if a thinner a dielectric layer is manufactured which has the necessary dielectric constant, the smaller the memory cell.
In metal oxide semiconductor ("MOS") technology, small, high performance transistors require thin gate and cell dielectrics. An ultrathin (.ltoreq.100 .ANG.) dielectric layer should minimally comprise enhanced dielectric properties.
However, several additional design considerations must be examined in the manufacture of ultrathin dielectric layers. These include uniformity in thickness, reliability, high dielectric constant, as well as imperviousness to electrical and thermal breakdown. Ultimately, high performance, ultrathin dielectric layers should also comprise a low diffusion rate for impurities, low interface state density, and chemical stability. Nevertheless, the physical constraints of the materials and methods of fabrication employed have made the characteristics of the dielectrics less than the optimum.
Silicon dioxide, at thicknesses greater than 100 .ANG., provides a cost effective, high quality dielectric layer for single crystal silicon, polycrystalline silicon ("polysilicon"), or amorphous silicon substrates. Nonetheless, for dielectric layers less than 100 .ANG., silicon dioxide is known to have a high defect density. Silicon dioxide also exhibits poor characteristics as a diffusion mask against impurities. Further, silicon dioxide has a relatively low dielectric constant.
In light the inherent limitations of silicon dioxide for dielectric layers of 100 .ANG. or less, several alternatives have been developed. One such alternative is the use of silicon nitride (Si.sub.3 N.sub.4) as a dielectric layer. This layer can be formed on a substrate surface through a process which includes Rapid Thermal Nitridation ("RTN"). Under RTN, the silicon substrate is exposed to either pure ammonia (NH.sub.3) or an ammonia plasma at temperatures approximately between 850.degree. C. and 1200.degree. C. to form a silicon nitride film.
Precise ultrathin dielectric layers are currently fabricated employing RTN. However, these layers have several shortcomings. RTN-type ultrathin dielectrics lack uniformity in their overall composition. Further, they have questionable reliability in part because of their susceptibility to high electrical leakage, as well as electrical and thermal breakdown. Hence, the overall cell capacitance of the known art is limited.
Moreover, current techniques for fabricating ultrathin dielectric layers, such as silicon nitride, have failed to address current leakage caused by the bulk effects of semiconductor wafers, also known as, pinholes. This problem is of significance where the dielectric layer is substantially in the 100 .ANG. range. A pinhole having a sufficient length enables current leakage, and as such, reduces the overall reliability of the device.
One solution to the problem of pinholes is to divide the dielectric layer having a specified thickness and dielectric constant into two comparable dielectric layers which have both a composite thickness and dielectric constant.
Referring to FIG. 1, a first dielectric layer 5 is illustrated superjacent a semiconductor substrate 1. First dielectric layer 5 comprises a pinhole 4. Superjacent first dielectric layer 5 is a second dielectric layer 9 comprising a pinhole 6. If both first and second dielectric layers, 5 and 9, are replaced with a single dielectric layer having an equivalent dielectric constant, a pinhole therein may be sufficient to cause electrical leakage.
However, by forming two independent dielectric layers, the probability is substantially reduced that both pinholes 4 and 6 are aligned in such a way as to create the potential for leakage.